A conventional power device includes a p type semiconductor layer and an n type semiconductor layer formed in a surface of a semiconductor substrate by ion implantation or impurity diffusion, and an insulating film and an electrode formed on surfaces of the p type semiconductor layer and the n type semiconductor layer. At a corner portion (electrode end portion) of the electrode of a power device having the basic configuration as described above, an electric field is easily concentrated. Accordingly, in order to mitigate the electric field concentration, at a position in contact with a termination portion of the electrode, an impurity region (hereinafter, referred to as guard ring (GR) layer) is formed in the semiconductor layer. Further, in order to mitigate the electric field concentration occurring at a corner portion (electrode end portion) of the GR layer by extension toward an inside of the semiconductor layer, another impurity region (hereinafter, referred to as junction termination extension (JTE) layer) is formed in the surface of the semiconductor layer outside the GR layer so as to be in contact with or apart from the GR layer.
FIG. 9 is a vertical cross-sectional view showing the electrode termination structure of the conventional power semiconductor device described in Patent Document 1, and more specifically, shows a vertical cross-sectional structure of a Schottky barrier diode including a GR layer and a plurality of JTE layers as a termination structure. As shown in FIG. 9, a first electrode 3P is formed as a Schottky electrode on a surface of an n− type semiconductor layer 2P on an n+ type semiconductor substrate 1P. In addition, a GR layer 4P formed of a first p type semiconductor layer is formed from the surface of the n− type semiconductor layer 2P toward an inside of the layer 2P so as to surround the first electrode 3P in a ring shape while being in contact with an end portion of the first electrode 3P. Moreover, from the surface of the n− type semiconductor layer 2P toward the inside of the layer 2P, a plurality of JTE layers 5P formed of a second p type semiconductor layer are formed so as to be positioned in a ring shape around the GR layer 4 while being apart from the GR layer 4P. A second electrode 6P is formed below a rear surface of the n+ type semiconductor substrate 1P as an Ohmic electrode. Further, an insulating film 7P is formed on part of the electrode 3P that includes the end portion of the first electrode 3P, on a surface of a portion of the GR layer 4 that extends from the end portion of the first electrode 3P toward an outside, on surfaces of the respective JTE layers 5P, and on a surface of the n− type semiconductor layer 2P.
As described above, the termination structure of FIG. 9 includes the GR layer 4P for mitigating an electric field at the end portion of the first electrode 3P, and a plurality of JTE layers 5P for mitigating electric field concentration at an end portion (corner portion) 4PE of the GR layer 4P.
The above-mentioned semiconductor device having the termination structure consisting of the GR layer 4P and the JTE layers 5P is capable of obtaining a breakdown voltage that is close to an ideal breakdown voltage calculated from a thickness and impurity concentration of the n− type semiconductor layer 2P.
Patent Document 1: Japanese Patent Application Laid-Open No. 2003-101039
However, in the termination structure in which the JTE layers 5 as shown in FIG. 9 are provided, an energy level or defect existing at an interface 8P between the n− type semiconductor layer 2P and the insulating film 7P, or a minute amount of adventitious impurities that infiltrate from the insulating film 7P through the interface 8P and a minute amount of adventitious impurities that infiltrate into the interface 8P from an outside through the insulating film 7P become a source and a breakdown point of a leakage current. As a result, the breakdown voltage deteriorates significantly in some cases.